Systemverilog
CheckedThis skill leverages SystemVerilog for simulating and verifying hardware designs, accelerating development and reducing errors in complex digital systems.
Install on your platform
Showing Claude Code. One command installs this skill into any of the agents below.
- 1
Run this in your project
terminal$ npx skills add mindrally/skills --skill systemverilog -a claude-code Uses the open-source
skillsCLI and needs Node.js. Add-gto install it for your user instead of this project.
What we know about this skill
Publisher
mindrally
Taken from the source listing. We haven't verified who controls this account.
Install target
Live repository
Not pinned. Installing fetches whatever the repository holds at the time you run the command.
Automated safety checks
This skill passed all 6 checks. We read its files at one commit and looked for the things that make a skill dangerous to run — not for whether it works.
Declares what it does: passed
SKILL.md parses and declares a name and a description.
SKILL.md exists, its frontmatter parses, and it declares a name and a description.
No undeclared network calls: passed
Makes no network calls.
Every host the skill dials — from its scripts, its config endpoints or the commands it tells the agent to run — is either well-known package and API infrastructure or declared in its own frontmatter. Links in documentation are not counted.
No obfuscated payloads: passed
No encoded or obfuscated payloads.
No base64, hex or compressed blob is decoded and then executed, and no encoded shell commands.
No credential access: passed
Reads no keys, tokens, keychains or credential files.
Neither the code nor the SKILL.md instructions read SSH keys, cloud credentials, keychains, token stores, browser cookie databases or dotfiles that hold secrets.
No pipe-to-shell installers: passed
No pipe-to-shell or download-and-run installers.
No `curl … | sh` pattern, in the code or in the instructions, that runs code fetched at run time.
Pinned to a commit: passed
Scanned mindrally/skills at 7682ca7771.
The exact upstream commit SHA that was scanned is recorded, so the result refers to specific bytes.
- Commit
- 7682ca7771
- Manifest
- systemverilog/SKILL.md
- Scanned
- 1 file, 77 lines
About this skill
The SystemVerilog skill enables AI agents to write, debug, and verify hardware description code using the industry-standard language for digital design. It supports complex modeling of sequential logic, concurrent processes, and verification environments essential for modern chip development.
When to use it
- Generating synthesizable RTL code for FPGA or ASIC implementation projects.
- Creating SystemVerilog Assertions (SVA) to define formal property checks within testbenches.
- Writing randomized stimulus generation scripts for automated functional verification.
- Debugging simulation errors by analyzing waveform data and constraint definitions.
Key capabilities
- Full syntax support for modules, interfaces, and packages.
- Implementation of class-based object-oriented design patterns.
- Generation of randomization constraints using the
randkeyword. - Support for verification methodologies including UVM component structures.
Example prompts
- "Create a SystemVerilog module for a 32-bit ALU with add, subtract, and shift operations."
- "Write a SystemVerilog assertion to check that the output never exceeds the maximum clock frequency limit."
- "Generate a testbench with randomized inputs to verify the functionality of a UART transmitter."
Tips & gotchas
Ensure your AI agent understands the distinction between synthesizable code and simulation-only constructs like initial blocks or $display. For complex verification tasks, explicitly request UVM component hierarchies to maintain industry-standard practices.